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Specifications ispLSI and pLSI 1032
ispLSI and pLSI 1032
(R) (R)
High-Density Programmable Logic Features
* HIGH-DENSITY PROGRAMMABLE LOGIC -- High Speed Global Interconnect -- 6000 PLD Gates -- 64 I/O Pins, Eight Dedicated Inputs -- 192 Registers -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Fast Random Logic -- Security Cell Prevents Unauthorized Copying * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 90 MHz Maximum Operating Frequency -- fmax = 60 MHz for Industrial and Military/883 Devices -- tpd = 12 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile E2CMOS Technology -- 100% Tested * ispLSI OFFERS THE FOLLOWING ADDED FEATURES -- In-System ProgrammableTM (ISPTM) 5-Volt Only -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping * COMBINES EASE OF USE AND THE FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Four Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispLSI AND pLSI DEVELOPMENT TOOLS pDS(R) Software -- Easy to Use PC WindowsTM Interface -- Boolean Logic Compiler -- Manual Partitioning -- Automatic Place and Route -- Static Timing Table ispDS+TM Software -- Industry Standard, Third Party Design Environments -- Schematic Capture, State Machine, HDL -- Automatic Partitioning and Place and Route -- Comprehensive Logic and Timing Simulation -- PC and Workstation Platforms
Functional Block Diagram
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0 A0 C7
Output Routing Pool
A2 A3 A4
Logic Array
DQ
C5
DQ
GLB
C4 C3
DQ
A5 A6 A7
C2 C1
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
C0
CLK
Output Routing Pool
Description
The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032 features 5-Volt insystem programming and in-system diagnostic capabilities. It is the first device which offers non-volatile "on-the-fly" reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1032 device, but multiplexes four of the dedicated input pins to control in-system programming. The basic unit of logic on the ispLSI and pLSI 1032 devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see figure 1). There are a total of 32 GLBs in the ispLSI and pLSI 1032 devices. Each GLB has 18 inputs, a programmable AND/OR/XOR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
February 1997 1996 ISP Encyclopedia
1996 ISP Encyclopedia
1032_02
1
Output Routing Pool
A1
DQ
C6
Specifications ispLSI and pLSI 1032
Functional Block Diagram
Figure 1. ispLSI and pLSI 1032 Functional Block Diagram
I/O I/O I/O I/O 63 62 61 60 RESET I/O I/O I/O I/O 59 58 57 56 I/O I/O I/O I/O 55 54 53 52 I/O I/O I/O I/O 51 50 49 48 IN IN 76
Input Bus Generic Logic Blocks (GLBs) D7 D6 Output Routing Pool (ORP) D5 D4 D3 D2 D1 D0
IN 5 IN 4 I/O 47 I/O 46 I/O 45 I/O 44
C7
I/O 0 I/O 1 I/O 2 I/O 3
A0 A1
Output Routing Pool (ORP)
C6
Output Routing Pool (ORP)
C5 C4 C3 C2 C1 C0
I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32
Input Bus
A3 A4 A5 A6 A7
I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *SDI/IN 0 *MODE/IN 1
Global Routing Pool (GRP)
B0
B1
B2
B3
B4
B5
B6
B7
Clock Distribution Network
Megablock
Output Routing Pool (ORP) Input Bus
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
*ispEN/NC *SDO/IN 2 *SCLK/IN 3 I/O I/O I/O I/O 16 17 18 19 I/O I/O I/O I/O 20 21 22 23 I/O I/O I/O I/O 24 25 26 27 I/O I/O I/O I/O 28 29 30 31 YYYY 0123
0139(1)-32-isp
*ISP Control Functions for ispLSI 1032 Only
The devices also have 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. Additionally, all outputs are polarity selectable, active high or active low. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. The I/O cells within the Megablock also share a common Output Enable (OE) signal. The ispLSI and pLSI 1032 devices contain four of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI and pLSI 1032 devices are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI and pLSI 1032 devices). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
2
lnput Bus
I/O 4 I/O 5 I/O 6 I/O 7
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Commercial TA = 0C to +70C TA = -40C to +85C TC = -55C to +125C MIN. 4.75 4.5 4.5 0 2.0 MAX. 5.25 5.5 5.5 0.8 Vcc + 1 V V
Table 2- 0005Aisp w/mil.eps
UNITS
VCC VIL VIH
Supply Voltage
Industrial Military/883
V
Input Low Voltage Input High Voltage
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input Capacitance I/O and Clock Capacitance Commercial/Industrial Military MAXIMUM1 8 10 10 UNITS pf pf pf TEST CONDITIONS V CC=5.0V, VIN=2.0V V CC=5.0V, VIN=2.0V V CC=5.0V, VI/O, VY=2.0V
Table 2- 0006
C1 C2
1. Guaranteed but not 100% tested.
Data Retention Specifications
PARAMETER Data Retention ispLSI Erase/Reprogram Cycles pLSI Erase/Reprogram Cycles MINIMUM 20 10000 100 MAXIMUM - - - UNITS Years Cycles Cycles
Table 2- 0008B
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See figure 2
Figure 2. Test Load
+ 5V R1 Device Output R2 CL* Test Point
3-state levels are measured 0.5V from steady-state active level.
Table 2- 0003
Output Load Conditions (see figure 2)
*CL includes Test Fixture and Probe Capacitance.
Test Condition A B Active High Active Low C Active High to Z at VOH - 0.5V Active Low to Z at VOL + 0.5V R1 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
470
470
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage IOL =8 mA IOH =-4 mA CONDITION MIN. - 2.4 - - - - - - - Industrial/Military TYP.3 - - - - - - - 130 135 MAX. 0.4 - -10 10 -150 -150 -200 190 220
UNITS V V A A A A mA mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1
ICC2,4
1. 2. 3. 4.
Input or I/O Low Leakage Current 0V VIN VIL (MAX.) Input or I/O High Leakage Current 3.5V VIN VCC isp Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current 0V VIN VIL (MAX.) 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V Commercial fTOGGLE = 1 MHz
One output at a time for a maximum duration of one second. Measured using eight 16-bit counters. Typical values are at VCC = 5V and TA = 25oC. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption secTable 2- 0007A-32-isp tion of this datasheet and Thermal Management section of this Data Book to estimate maximum ICC.
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Specifications ispLSI and pLSI 1032
External Timing Parameters
Over Recommended Operating Conditions
52 PARAMETER TEST #
COND.
DESCRIPTION1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback (tsu2 1 tco1) + Clock Frequency, Max Toggle 4 GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock - -
-90
12 17 - - - - 8 - - - - - -
-80
15 20 - - - - - - - - - -
-60
20 25 - - - - 13 - - 16 - 22.5 - 24 24 - - - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
MIN. MAX. MIN. MAX. MIN. MAX. 1 2 3 4 5 6 7 8 9
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5
1. 2. 3. 4. 5.
A A A - - - A - - - - A - B C - - - -
S
S
10 12 17 18 18 - - - -
90.9 58.8 125 6 - 0 9 - 0 - - - 4 4 2 6.5
80 50 7 - 0 - 0 - - - 5 5 2 6.5 100
60 38 83 9 - 0 13 - 0 - 13 - - 6 6 2.5 8.5
USE 1032E-80 FOR NEW DESIG N
10 15 15 15 - - - - 10
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Ext. Sync. Clock Pulse Duration, High 17 Ext. Sync. Clock Pulse Duration, Low 18 I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) 19 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
Unless noted otherwise, all parameters use a GRP load of 4 GLBs, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-Bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section.
USE 1032E-70 FOR NEW DESIG N
10 10
Table 2-0030-32/90,80,60C
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Internal Timing Parameters1
2
PARAMETER
#
DESCRIPTION
-90
-80
-60
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
USE 1032E-80 FO R NEW DESIGNS
23 24 25 26
I/O Register Hold Time after Clock I/O Register Clock to Out Delay I/O Register Reset to Out Delay Dedicated Input Delay
2.1 - - -
-
1.0 - - -
USE 1032E-70 FO R NEW DESIGNS
Inputs tiobp tiolat tiosu tioh tioco tior tdin GRP tgrp1 tgrp4 tgrp8 tgrp12 tgrp16 tgrp32 GLB t4ptbp t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgr tptre tptoe tptck ORP torp torpbp
20 21 22
I/O Register Bypass I/O Latch Delay I/O Register Setup Time before Clock
- - 4.8
1.6 2.4 - 2.4 2.8 3.2
- - 5.5
2.0 3.0 - - 3.0 2.5 4.0
- - 7.3 1.3 - - -
2.7 4.0 - - 4.0 3.3 5.3
ns ns ns ns ns ns ns
27 28 29 30 31 32
GRP Delay, 1 GLB Load GRP Delay, 4 GLB Loads GRP Delay, 8 GLB Loads GRP Delay, 12 GLB Loads GRP Delay, 16 GLB Loads GRP Delay, 32 GLB Loads
- - - - - -
1.2 1.6 2.4 3.0 3.6 6.4
- - - - - -
1.5 2.0 3.0 3.8 4.5 8.0
- - - - - -
2.0 2.7 4.0 5.0 6.0 10.6
ns ns ns ns ns ns
33 34 35 36 37 38 39 40 41 42 43 44
4 Product Term Bypass Path Delay 1 Product Term/XOR Path Delay 20 Product Term/XOR Path Delay XOR Adjacent Path Delay3 GLB Register Bypass Delay GLB Register Setup Time before Clock GLB Register Hold Time after Clock GLB Register Clock to Output Delay GLB Register Reset to Output Delay GLB Product Term Reset to Register Delay GLB Product Term Output Enable to I/O Cell Delay GLB Product Term Clock Delay
- - - - -
5.2 5.7 7.0 8.2 0.8 - -
- - - - -
6.5 7.0 8.0 9.5 1.0 - -
- - - - - 1.3 6.0 - - - - 4.6
8.6 9.3 10.6 12.7 1.3 - - 2.7 3.3 13.3 12.0 9.9
ns ns ns ns ns ns ns ns ns ns ns ns
1.2 3.6 - - - - 2.8
1.0 4.5 - - - - 3.5
1.6 2.0 8.0 7.8 6.0
2.0 2.5 9.0 7.5
10.0
45 46
ORP Delay ORP Bypass Delay
- -
2.4 0.4
- -
2.5 0.5
- -
3.3 0.7
ns ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Internal Timing Parameters1
2
PARAMETER
#
DESCRIPTION
-90
-80
-60
UNITS
Outputs tob toen todis Clocks tgy0 tgy1/2 tgcp tioy2/3 tiocp
USE 1032E-8 FOR NEW DE 0 SIGNS USE 1032E-7 FOR NEW DE 0 SIGNS
- - - 2.4 4.0 4.0 - - - 3.0 5.0 5.0
MIN. MAX. MIN. MAX. MIN. MAX.
47 48 49
Output Buffer Delay I/O Cell OE to Output Enabled I/O Cell OE to Output Disabled
- - -
4.0 6.7 6.7
ns ns ns
50 51 52 53 54
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) Clock Delay, Y1 or Y2 to Global GLB Clock Line Clock Delay, Clock GLB to Global GLB Clock Line Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line Clock Delay, Clock GLB to I/O Cell Global Clock Line
3.6 2.8 0.8 2.8 0.8
3.6 4.4 4.0 4.4 4.0
4.5 3.5 1.0 3.5 1.0
4.5 5.5 5.0 5.5 5.0
6.0 4.6 1.3 4.6 1.3
6.0 7.3 6.6 7.3 6.6
ns ns ns ns ns
Global Reset tgr 55
Global Reset to GLB and I/O Registers
-
8.2
-
9.0
-
12.0
ns
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
ispLSI and pLSI 1032 Timing Model
I/O Cell GRP Feedback Ded. In GLB ORP I/O Cell
#26 I/O Reg Bypass #20 Input D Register Q RST #21 - 25 GRP 4 #28 GRP Loading Delay #27, 29, 30, 31, 32 4 PT Bypass #33 20 PT XOR Delays #34, 35, 36 #55 D RST #38, 39, 40, 41 GLB Reg Bypass #37 GLB Reg Delay Q ORP Bypass #46 ORP Delay #45 #47 I/O Pin (Output) #48, 49
I/O Pin (Input)
#55 Reset
Clock Distribution Y1,2,3 #51, 52, 53, 54 #50
Control RE PTs OE #42, 43, CK 44
Y0
Derivations of tsu, th and tco from the Product Term Clock1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) = (#20 + #28 + #35) + (#38) - (#20 + #28 + #44) 5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5) = Clock (max) + Reg h - Logic = (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#20 + #28 + #44) + (#39) - (#20 + #28 + #35) 4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)
th
tco
= Clock (max) + Reg co + Output = (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) = (#20 + #28 + #44) + (#40) + (#45 + #47) 19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)
Derivations of tsu, th and tco from the Clock GLB1
tsu
= Logic + Reg su - Clock (min) = (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) = (#20 + #28 + #35) + (#38) - (#50 + #40 + #52) 5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0) = Clock (max) + Reg h - Logic = (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) = (#50 + #40 + #52) + (#39) - (#20 + #28 + #35) 4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)
th
tco
= Clock (max) + Reg co + Output = (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) = (#50 + #40 + #52) + (#40) + (#45 + #47) 19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0) 1. Calculations are based upon timing specifications for the ispLSI and pLSI 1032-80.
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Maximum GRP Delay vs GLB Loads
6 5 ispLSI and pLSI 1032-60 ispLSI and pLSI 1032-80 ispLSI and pLSI 1032-90
GRP Delay (ns)
4 3 2 1 0 4 8 GLB Loads 12 16
0126A-80-32-isp
Power Consumption
Power consumption in the ispLSI and pLSI 1032 device depends on two primary factors: the speed at which the device is operating, and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax
250
used. Figure 3 shows the relationship between power and operating speed.
ICC (mA)
200 150 100 50 0 10 20 30
ispLSI and pLSI 1032
40
50
60
70
80
fmax (MHz)
Notes: Configuration of eight 16-bit Counters Typical Current at 5V, 25C
ICC can be estimated for the ispLSI and pLSI 1032 using the following equation: ICC = 52 + (# of PTs * 0.30) + (# of nets * Max. freq * 0.009) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of 2 GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A-32-80-isp
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
In-System Programmability
The ispLSI devices are the in-system programmable versions of the Lattice Semiconductor High-Density programmable Large Scale Integration (pLSI) devices. By integrating all the high voltage programming circuitry onchip, programming can be accomplished by simply shifting data into the device. Once the function is programmed, the non-volatile E2CMOS cells will not lose the pattern even when the power is turned off. All necessary programming is done via five TTL level logic interface signals. These five signals are fed into the on-chip programming circuitry where a state machine Figure 4. ISP Programming Interface controls the programming. The interface signals are isp Enable (ispEN), Serial Data In (SDI), Serial Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control. Figure 4 illustrates the block diagram of one possible scheme for programming the ispLSI devices. For details on the operation of the internal state machine and programming of the device please refer to the ISP Architecture and Programming section in this Data Book. The device identifier for the ispLSI 1032 is 0000 0011 (03 hex). This code is the unique device identifier which is generated when a read ID command is performed.
SDO SDI MODE SCLK ispEN
5-wire ISP Programming Interface
ispEN SCLK MODE
SCLK MODE
SCLK MODE
ispEN SCLK MODE
ispLSI
SDI SDO
ispGAL
SDI SDO
ispGDS
SDI SDO SDI
ispLSI
SDO
0294B
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
ispLSI 1032 Shift Register Layout
D A T A D A T A
Data In (SDI)
159... 319...
High Order Shift Register Low Order Shift Register
...0 ...160 107 . . .
SDO SDI
E2CMOS Cell Array
Address Shift Register
. . . 0 SDO
Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification. A logic "0" disables it.
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Specifications ispLSI and pLSI 1032
Pin Description
Name
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 IN 4 - IN 7 ispEN*/NC
PLCC Pin Numbers
26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15, 67, 23 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4, 8, 12, 16, 84, 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, 2, 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18 19
Description
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device.
SDI*/IN 0
25
MODE*/IN 1
42
SDO*/IN 2
44
SCLK*/IN 3
61
RESET Y0 Y1
24 20 66
Y2
63
Y3
62
GND
VCC
* For ispLSI 1032 Only
1, 21,
22, 65
43,
64
Ground (GND) VCC
Table 2-0002A-32-isp
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Pin Description
Name
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 IN 4 - IN 7 ispEN*/NC
TQFP Pin Numbers
17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 6, 66, 14 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 3, 7, 87, 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8, 89, 20, 28, 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9 10
Description
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. These pins are not used.
SDI*/IN 0
16
MODE*/IN 1
37
SDO*/IN 2
39
SCLK*/IN 3
60
NC
1, 26, 51, 76, 15 11 65
2, 27, 52, 77,
24, 49, 74, 99,
25, 50, 75 100
RESET Y0 Y1
Y2
62
Y3
61
GND
VCC
* For ispLSI 1032 Only
13, 12,
38, 64
63,
88
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. Ground (GND) VCC
Table 2- 0002B-32-isp
13
1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Pin Description
Name
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 IN 4 - IN 7 ispEN*/NC
CPGA Pin Numbers
F1, K1, K3, L4, L7, K8, L11, J11, E9, B11, B9, A8, A5, B4, A1, C1, H1, J2, L2, J5, K7, L9, K10, H10, D11, C10, A10, B6, B5, A3, B2, D2, H2, L1, L3, K5, L6, L10, J10, H11, D10, A11, A9, B7, C5, A2, C2, D1, A6, J1, K2, K4, L5, L8, K9, K11, F10, C11, B10, B8, A7, A4, B3, B1, E3 E2
Description
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
E10, C7, G3
Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output - This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input - This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. This pin should be left floating or tied to VCC. This pin should never be tied to GND.
SDI*/IN 0
G2
MODE*/IN 1
K6
SDO*/IN 2
J7
SCLK*/IN 3
G10
RESET Y0 Y1
G1 E1 E11
Y2
G9
Y3
G11
NC
G3
GND
VCC
C6, F2,
F3, F11
F9,
J6
Ground (GND) VCC
Table 2-0002-32/883
14
1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Pin Configuration
ispLSI and pLSI 1032 84-Pin PLCC Pinout Diagram
I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 74 73 72 71 70 69 68 67
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 VCC GND *ispEN/NC RESET *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *MODE/IN 1 GND *SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 IN 4 Y1 VCC GND Y2 Y3 IN 3/SCLK* I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25
ispLSI 1032 pLSI 1032
Top View
66 65 64 63 62 61 60 59 58 57 56 55 54
*Pins have dual function capability for ispLSI 1032 only (except pin 23, which is ispEN only).
0123-32-isp
15
1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Pin Configuration
ispLSI and pLSI 1032 100-pin TQFP Pinout Diagram
NC NC I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 VCC GND *ispEN/NC RESET *SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC NC I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND IN 5 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
ispLSI 1032 pLSI 1032
Top View
NC NC I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 IN 4 Y1 VCC GND Y2 Y3 IN 3/SCLK* I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC NC
*Pins have dual function capability for ispLSI 1032 only (except pin 14, which is ispEN only).
0766A-32-isp
NC NC I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *MODE/IN1 GND *SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 NC NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
16
1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Pin Configuration
ispLSI and pLSI 1032/883 84-Pin CPGA Pinout Diagram
11
I/O38
10
I/O41
9
I/O42
8
I/O44
7
I/O47
6
IN6
5
I/O48
4
I/O51
3
I/O53
2
I/O54
1
I/O56
PIN A1
A
I/O36
I/O39
I/O40
I/O43
I/O46
I/O45
I/O49
I/O52
I/O55
I/O57
I/O59
B
I/O35
I/O37
IN5
GND
I/O50
INDEX
I/O58
I/O60
C
I/O33
I/O34
I/O61
I/O62
D
Y1
IN4
I/O32
Vcc
I/O31
GND
ispLSI 1032/883 pLSI 1032/883
Bottom View
I/O63
IN7
Y0
E
GND
Vcc
I/O0
F
Y3
*SCLK/ IN3
Y2
*ispEN /NC
*SDI/ IN0
RESET
G
I/O30
I/O29
I/O2
I/O1
H
I/O28
I/O26
*SDO/ IN2
GND
I/O13
I/O5
I/O3
J
I/O27
I/O25
I/O23
I/O20
I/O17
*MODE/ IN1
I/O14
I/O11
I/O8
I/O7
I/O4
K
I/O24
I/O22
I/O21
I/O19
I/O16
I/O18
I/O15
I/O12
I/O10
I/O9
I/O6
L
*Pins have dual function capability for ispLSI 1032/883 only (except pin G3, which is ispEN only).
0488A-32-isp/883
17
1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1032
Part Number Description
(is)pLSI
Device Family
1032 - XX
X
X
X
Grade Blank = Commercial I = Industrial /883 = 883 Military Process Package J = PLCC T = TQFP G = CPGA Power L = Low
0212-80B-isp1032
Device Number
Speed 90 = 90 MHz fmax 80 = 80 MHz fmax 60 = 60 MHz fmax
ispLSI and pLSI 1032 Ordering Information
COMMERCIAL Family
fmax (MHz) tpd (ns)
90 90 12 12 15 15 20 20 12 12 15 15 20 20
Ordering Number ispLSI 1032-90LJ ispLSI 1032-90LT ispLSI 1032-80LJ ispLSI 1032-80LT ispLSI 1032-60LJ ispLSI 1032-60LT pLSI 1032-90LJ pLSI 1032-90LT pLSI 1032-80LJ pLSI 1032-80LT pLSI 1032-60LJ pLSI 1032-60LT
Package 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP
ispLSI
80 80 60 60 90 90 80
pLSI 80 60 60
INDUSTRIAL Family ispLSI 60 pLSI 60
fmax (MHz) tpd (ns)
60 20 20 20
Ordering Number ispLSI 1032-60LJI ispLSI 1032-60LTI pLSI 1032-60LJI
Package 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC
MILITARY/883 Family ispLSI pLSI
fmax (MHz) tpd (ns)
60 60 20 20
Ordering Number ispLSI 1032-60LG/883 pLSI 1032-60LG/883
SMD Number 5962-9308501MXC 5962-9466801MXC
Package 84-Pin CPGA 84-Pin CPGA
Table 2- 0041A-32-isp
Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended.
18
1996 ISP Encyclopedia
Copyright (c) 1997 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispDS, ispDS+, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders. Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right. The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. LSC warrants performance of its products to current and applicable specifications in accordance with LSC's standard warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. LSC assumes no liability for applications assistance, customer's product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such applications is prohibited. LATTICE SEMICONDUCTOR CORPORATION 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Tel.: (503) 681-0118 FAX: (503) 681-3037 http://www.latticesemi.com
February 1997

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